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wildzzz 8 hours ago [-]
By adding a bunch of IP blocks that do stuff the open ISA doesn't, like peripherals or multicore processing. It also helps if you can make it high throughout, low latency, or low power by adjusting some "knobs".
RealityVoid 8 hours ago [-]
The article is quite weak, to be honest. Which is a shame, sillicon IP design is quite an interesting domain and it would deserve better coverage.
I was pleasantly surprised it's a startup done by two of my conationals.
johncole 3 hours ago [-]
Thanks, how could I have made it stronger?
LeonKnst 4 hours ago [-]
The credibility point is the most interesting part of this. In semiconductors, having a good design seems secondary to convincing customers that you'll still be around to support it years later. RISC-V lowers the barrier to building a CPU, but i'm not sure it lowers the trust barrier nearly as much.
inigyou 3 hours ago [-]
I'm not so sure of that. Don't companies often buy a million of a chip and then that's it? Famously the MacBook Neo was created to get rid of some stockpile of old chips Apple was sitting on.
rcxdude 37 minutes ago [-]
It depends on the industry. High-volume consumer electronics is often like this (they're making this year's product, they roughly know the demand, they'll be redesigning it in a year or two), but industrial electronics generally wants to know that they will still be able to buy the parts in 10 years, at least (a design or even a single unit can be in active use for decades).
Palomides 43 minutes ago [-]
numerically, most companies are not in cutting edge rapid product cycle consumer gear like apple, they instead want to buy 1000/year of the same part for a decade (or maybe gradually better, compatible equivalents)
johncole 3 hours ago [-]
I think this story is the exception. The supply chain time for hardware is so long, designers are picking their chips out months and years in advance. So you really do have to trust that the supplier will be around to support the hardware in a few months or a few years.
inigyou 2 hours ago [-]
Separately from my other comment, European companies seem to have a credibility problem no matter what they do or how well they do it, just because they're outside of the good old boy's club that is Silicon Valley. When's the last time you heard some praise for OVH or IONOS Cloud?
mcshicks 2 hours ago [-]
Umm I would say working physical samples is pretty important.
akoboldfrying 8 hours ago [-]
The HN article title suggests a contradiction where there isn't one. The instruction set is just the spec -- the high-level contract that the silicon must implement, with many important details like cycle counts per instruction left unspecified. It implies very little about how you would actually implement the inner workings, which could be done in an almost infinite number of different ways (including simulating them on some completely different architecture). Compare "How do you sell a calculator design when the rules of arithmetic are free?"
userbinator 7 hours ago [-]
RISC-V is pretty unoptimisable though; the industry has had its fair share of pretty lackluster MIPS and MIPS-like clones in embedded, and they've been mainly high-volume low-cost "cheap and good enough" SoCs. To be competitive with ARM and x86 you really need higher code density and better, more complex instructions.
joha4270 7 hours ago [-]
To be competitive with ARM and x86 they need a talented design team creating fast and wide cores on a modern node. (which I expect to take a decade at least)
For the vast majority of non-number-crunching code any theoretical difference between instruction sets vanishes in the noise of core design.
camel-cdr 2 hours ago [-]
RISC-V has higher code density than Arm and x86 and all three have a comparible uop density, but RISC-V has a slightly higher average instruction count.
What more complex instructions are missing?
ithkuil 7 hours ago [-]
Genuine question: what makes ARM64 a denser ISA compared to RISC-V ?
akoboldfrying 5 hours ago [-]
> RISC-V is pretty unoptimisable though
Is it? So there's no scope for different levels of pipelining, out-of-order execution with various numbers of execution units, branch prediction of various levels of sophistication, L1 cache of various amounts, multiplication and division implemented in various ways from slow but low chip area and power consumption to fast with high chip area or power consumption? Because those are all things that have major performance impact even on plain "RISC-style" x86-64 code.
I was pleasantly surprised it's a startup done by two of my conationals.
For the vast majority of non-number-crunching code any theoretical difference between instruction sets vanishes in the noise of core design.
Is it? So there's no scope for different levels of pipelining, out-of-order execution with various numbers of execution units, branch prediction of various levels of sophistication, L1 cache of various amounts, multiplication and division implemented in various ways from slow but low chip area and power consumption to fast with high chip area or power consumption? Because those are all things that have major performance impact even on plain "RISC-style" x86-64 code.